Choosing an FPGA Vendor and Family: AMD/Xilinx, Intel/Altera, Lattice, Microchip, Gowin

Choosing an FPGA vendor comes down to four things: what the chip actually contains, whether it has the resources and pins your board needs, how good the vendor's tools and documentation are, and whether the family will still be in production when your product needs a respin. Xilinx vs Altera used to be the whole conversation. It no longer is. InTechHouse has delivered project work on AMD/Xilinx, Intel/Altera, Microchip and Lattice devices, and this guide walks through the criteria we use to make that call.

Key Takeaways

• The FPGA market is no longer a two-vendor question. Xilinx vs Altera has widened to include Lattice, Microchip and Gowin.
• Four criteria decide a family: what is on the chip, whether resources and package fit the board, toolchain and documentation quality, and long-term availability.
• InTechHouse has delivered project work on AMD/Xilinx, Intel/Altera, Microchip and Lattice families. No Gowin project to date.
• Vendor toolchains (Vivado, Vitis, Quartus, Lattice Radiant, Lattice Diamond) do not transfer skill between vendors. Budget time for the learning curve when moving from one family to another.
• On a current rail project, InTechHouse is selecting the vendor and the device using this same framework, working with the customer before the architecture is fixed.

Xilinx vs Altera Is No Longer the Question

Altera was acquired by Intel, and shortly afterward AMD took Xilinx. Those two deals produced the largest competing brands in the FPGA market, which is why "xilinx vs altera" and "amd vs intel fpga" are, in practice, the same search: two questions about the same rivalry, asked under two generations of branding.

That rivalry is no longer the whole picture. Lattice, Microchip and Gowin now compete for real projects, each with a distinct position: lower cost, lower power, or a specific niche such as security-oriented designs. A team picking a family today has five vendors to weigh, not two, and the right answer depends on what the design actually needs rather than which of the two big names sounds more familiar.

This guide covers four selection criteria that hold regardless of vendor: what is built into the chip, whether the resources and package fit the board, how good the tools and documentation are, and how long the family will stay in production. It also covers what the vendors' tools cost a team in practice, and where InTechHouse stands: not neutral, but not one-vendor either.

The FPGA Market and Who the Vendors Are Now

Across all five vendors, a family is ultimately measured on the same three things: logic capacity, I/O count and speed. What differs is how each vendor packages those three around its own architecture and its own target market.

AMD/Xilinx. The Artix and Kintex families cover cost-optimized and mid-range designs, while the Zynq line (Zynq-7000 and Zynq UltraScale+) pairs FPGA fabric with a hard processor system, making it the default choice for designs that need Linux or a real-time OS running alongside programmable logic.

Intel/Altera. Intel MAX 10 and Intel Cyclone sit at the low-cost, low-power end, with Arria 10 and larger Agilex devices further up the range for higher-performance and data-center-adjacent work. In September 2025, Silver Lake completed the acquisition of a 51% stake in Altera from Intel, which retains the remaining 49% and continues to supply foundry capacity (Intel, 2025). Altera now operates as an independent FPGA company rather than an Intel business unit. For a design already in production, this changes the corporate structure behind the parts, not the parts themselves, and it is worth checking the current lifecycle documentation for any Altera family before committing to it long term.

Lattice. Built around small, low power fpgas with instant-on configuration, aimed at glue logic, sensor interfacing and applications where ultra low power consumption and board space matter more than raw density.

Microchip. PolarFire sits in the mid-to-high range with a focus on power efficiency and security features, positioned for industrial and communications designs that need more than a low-end part but do not need a data-center-class device.

Gowin. A newer, cost-driven entrant competing mainly in the low power fpgas and cost-sensitive segment, an alternative for designs where budget per unit is the dominant constraint.

What InTechHouse Has Actually Shipped On

Most FPGA design companies work with one vendor's tools and describe the rest of the market in general terms. InTechHouse has delivered project work across four of the five vendors above.

On AMD/Xilinx, that includes the Artix and Kintex families through UltraScale+, plus Zynq-7000 and Zynq UltraScale+, which is where most of our FPGA project volume sits. On Intel/Altera, we have worked with MAX 10 and Arria 10; these are older Altera families rather than a claim to current-generation Agilex expertise, and we present them that way here. On Microchip, we have delivered on PolarFire. On Lattice, on MachXO3. We have no Gowin project to date, and we are naming that gap deliberately: a vendor worth mentioning as a market option is also a vendor we should be honest about not having used.

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On the rail project we are currently running for a UK rail supplier, InTechHouse is the party selecting both the vendor and the device, working from the same four criteria covered below. The shape of our experience is breadth across four vendors and depth on Zynq, and it is worth being precise about that rather than rounding it up to something it is not.

Four Criteria That Actually Decide an FPGA Family

Before any vendor comparison, most candidates are already eliminated by a simpler filter: a device reasonably priced, that meets the project's requirements, and that leaves headroom for the design to grow. Specific requirements narrow it further. Wanting a particular amount of memory inside the device, rather than on a separate chip, is a common one. The four criteria below are what that filter is actually checking.

1. What Is on the Chip: Fabric, Processors and Hard Blocks

This is the most concrete axis, and the first thing to check against a design's requirements. Zynq UltraScale+, for example, combines programmable logic fabric, graphics capability and two processor types on one chip: Cortex-A cores for application-level software and Cortex-R cores for real-time tasks. Comparable combined families exist on the Intel/Altera side, some built on Cortex cores, while Lattice families are built around RISC-V.

Beyond the processors, the hard blocks decide whether a family can do the job at all: DSP slices and DSP blocks for multiply-accumulate operations, block RAM for on-chip storage, phase locked loops for clock generation, external memory interfaces, and hard peripheral blocks such as gigabit ethernet or a PCIe interface. Where a family has no hard processor core, soft processors implemented in the fabric itself can fill the gap, at the cost of logic resources that would otherwise go to the application.

2. Resources, Pins and Package

Once the on-chip content is right, the datasheet numbers that actually decide fit are logic cells or adaptive logic modules and the logic densities available across the family, plus block memory and DSP count. Physical constraints eliminate more designs than raw logic count does: the number of fpga pins and whether higher pin counts are available in the package you need, the fpga package itself and its signal integrity consequences at board level, how many separate power supplies the device requires, and the overall power budget.

Power supply count varies enormously by class of device. A single-supply Intel MAX 10 needs only one external 3.0V or 3.3V rail, which an internal on-die regulator then steps down to 1.2V for the core, so the board-level power design stays simple (Intel, 2024). A Zynq UltraScale+ MPSoC sits at the other end of that range: a reference power design for the baseline MPSoC family calls for 17 separate configurable rails, and the figure climbs past 30 on the RFSoC variants once RF data converters are added (Texas Instruments, 2020). At the low-power end, Lattice's iCE40 UltraPlus family is built for single-digit-microamp-class standby behavior, with a typical standby current in the order of 100µA in the vendor's own datasheet figures (Lattice Semiconductor, 2024), which is what makes it a common choice for always-on, battery-powered glue logic. Whichever family you are sizing, the number of rails and the standby figures belong in the board-level power budget before anything else.

Configuration method matters too. SRAM-based FPGAs load their configuration from external configuration memory at every power up, while flash-based parts hold configuration on the device and start instantly, which matters for applications where boot time is a requirement rather than an inconvenience. And the headroom point from above is worth repeating here specifically: buying exactly enough fabric for today's function is how a project pays twice, because the next feature forces a device change, and a device change usually forces a board change with it.

3. The Vendor's Development Tools and Documentation

This is the layer most comparison content skips, because vendors will not write it and single-vendor shops cannot.

"The second very important layer in any FPGA design is what tools and source materials the manufacturer provides. That matters a great deal, because the whole workflow splits into what we do in the FPGA logic and then how we load software onto it, and with which tools. Many of these tools work the way they work, there are plenty of bugs, they are in constant development. You have to learn it, and you have to know what works at one manufacturer and does not at another."

Adam Szychulec, Head of Hardware / Embedded, InTechHouse

The practical consequence is that toolchain familiarity is a per-vendor cost, not a transferable skill. A team that knows one vendor's flow well is not automatically fast on another vendor's flow, and that learning curve belongs in the project budget, not treated as a rounding error. Licensing follows a similar pattern across the industry: free or device-limited editions exist alongside paid ones, and open source tools cover a real but narrow part of the workflow.

InTechHouse works day to day in Vivado, Vitis, Quartus, Lattice Radiant and Lattice Diamond. On the AMD/Xilinx side, Vivado handles the hardware design and configuration flow while Vitis targets software-level acceleration on top of it. On the Intel/Altera side, Quartus Prime ships in three editions (Pro, Standard and Lite), with the Lite edition free to download and, notably, still including the built-in Signal Tap logic analyzer for on-chip debugging over JTAG, with no separate lab equipment required (Intel, 2025). That kind of built-in tooling is exactly the sort of detail that only shows up once a team is actually using the flow day to day, which is the point of this section. This section is as relevant to an engineer who already works mainly in one of these and is evaluating a move to another as it is to a system architect choosing a family for the first time; the tooling cost of that move is exactly what this criterion is meant to surface.

4. Long-Term Availability

This is the criterion most vendor-neutral comparison content leaves out, and it answers one of the most common buyer questions directly: will this family still be available when the product needs a respin, five or ten years from now?

The mechanism is simple: families adopted by military and space programs tend to stay in production far longer than consumer-oriented parts, because those programs commit to decades of support. Some FPGA families run for twenty to thirty years; Spartan-3 is a case in point, introduced in the early 2000s and only now being withdrawn, a lifespan no general-purpose processor family matches. Some vendors publish formal lifecycle commitments for product lines aimed at industrial, defense and aerospace markets specifically, which is worth checking directly with the vendor for any family under serious consideration.

FPGA Architecture Comparison: What the Vendors Build Differently

One reason vendor comparisons go wrong is that the numbers on two datasheets are not actually measuring the same thing. AMD/Xilinx builds its fabric from Configurable Logic Blocks (CLBs); the Altera lineage groups its fabric into Logic Array Blocks (LABs), each built from Adaptive Logic Modules (ALMs). The counting units differ enough that "logic cells" at one vendor and "logic elements" at another are not directly comparable quantities, and stacking the logic densities side by side without adjusting for that gives a misleading picture.

The same caution applies to DSP slices and block RAM, where granularity differs by vendor and sometimes by family within a vendor. Routing architecture is another axis where the vendors simply build differently: AMD/Xilinx fabric routes through a switch-matrix interconnect, while Intel's HyperFlex architecture, used in the high-end Stratix 10 and Agilex families rather than in MAX 10 or Arria 10, adds fine-grained registers throughout the routing fabric specifically so the place-and-route tool can retime a design for higher clock frequencies (Intel, 2023). It is a real architectural difference, and it is specific to those top-end families, not a property of the Altera lineage as a whole.

In practice, the way around comparing any of this directly is not a conversion table, since the ratio shifts by family and generation. It is to size against a known reference design close to the target application, or to synthesize the actual digital logic for the candidates under evaluation and read the resulting resource report directly.

Choosing by Job Shape: Glue Logic, Mid-Range, High Performance

The four criteria above turn into practical shortlists once you describe the job rather than the vendor.

Glue logic and I/O expansion with instant-on requirements. Small, flash-based, low power fpgas, where ultra low power consumption and boot time matter more than raw density. This is Lattice's core territory.

Motor control and moderate signal processing. Mid-range parts with enough DSP resources and either a hard processor or a capable soft processor, sized for a control loop rather than a data-center workload.

High-performance work with high-speed serial links. Larger devices with transceivers and high speed connectors on the board, which brings a higher power budget and a higher unit cost along with the performance.

A first FPGA project with no in-house experience. Here the dominant criterion is not silicon at all, it is toolchain and documentation quality, which is the third criterion above restated in the place where a first-time team can actually act on it: pick the family whose tools and reference material your team can learn fastest, not the family with the biggest number on the datasheet.

FPGA Boards: Prototype Early, on the Family You Intend to Ship

A large share of the search interest around this topic is really about development boards, so it is worth answering directly. The rule that matters: prototype early, on the family you actually intend to ship, not on whichever board happens to be in the drawer. What you are really evaluating during prototyping is the toolchain, the primitives, and where the design is likely to fail, and none of that carries over cleanly from a different vendor's board.

When choosing the right development board, match board features to your actual interfaces rather than buying the most capable option available: high speed connectors for any serial links the design needs, gigabit ethernet if networking is part of the product, adequate external memory, and flash memory for configuration if the target device is flash-based. Boards sold directly by AMD/Xilinx or by Intel typically cost more than third-party equivalents, but they usually come with better reference designs, which for a first project is often the thing that actually saves time.

Where the FPGA Market Is Going That This Page Is Not About

A large part of current vendor marketing sits around data centers, data center acceleration and accelerated computing, including adaptive compute acceleration platform devices that combine programmable fabric with hardened compute engines for AI workloads. There is also a substantial market in embedded vision and automotive applications. That is where a lot of vendor investment is actually going, and it is a different buyer from the embedded product teams this guide is written for: teams building industrial, aerospace, rail or life-science hardware that has to certify, survive a harsh environment, and stay in production for years. Worth knowing about, not the focus here.

How We Make This Decision on a Live Project

The four criteria above are not theoretical. On a current project for a UK rail supplier, InTechHouse is selecting both the vendor and the device, working within the same cost, requirements and headroom constraint covered earlier, with the project's specific requirements narrowing the field further from there. That selection is made together with the customer, early, before the architecture is fixed, rather than handed over as a finished recommendation.

Choosing a family for a new design? Request an FPGA architecture assessment.

InTechHouse case study: FPGA vendor and device selection for a public transport manufacturer application

A public transport manufacturer engaged InTechHouse during the early architecture phase of a new embedded system, before any FPGA vendor or device had been chosen. InTechHouse ran the selection against the project's cost, resource and headroom constraints together with the customer's specific interface and memory requirements, weighing candidates across multiple vendor families rather than defaulting to a single incumbent platform. The engagement is ongoing.